Publications

2021

ETP4HPC Petar Radojković (BSC), Paul M. Carpenter (BSC), Pouya Esmaili-Dokht (BSC), Rémy Cimadomo (UPMEM), Henri-Pierre Charles (CEA), Abu Sebastian (IBM), Paolo Amato (Micron). "Processing in Memory: The Tipping Point". European Technology Platform for High-Performance Computing (ETP4HPC). White Paper. July 2021.
ACM TESC Kazi Asifuzzaman, Rommel Sánchez Verdejo, Petar Radojković. "Performance and Power Estimation of STT-MRAM Main Memory with Reliable System-level Simulation". ACM Transactions on Embedded Computing Systems, Vol. 1, No. 1, Article 1. Publication date: January 2021.

2020

SC Isaac Boixaderas, Darko Zivanovic, Sergi Moré, Javier Bartolome, David Vicente, Marc Casas, Paul M. Carpenter, Petar Radojković, Eduard Ayguadé. "Cost-Aware Prediction of Uncorrected DRAM Errors in the Field". In Proceedings of the International Conference for High Performance Computing, Networking, Storage, and Analysis (SC). November 2020.
ResilientHPC.eu Petar Radojković, Manolis Marazakis, Paul Carpenter, Reiley Jeyapaul, Dimitris Gizopoulos, Martin Schulz, Adria Armejach, Eduard Ayguade, Francois Bodin, Ramon Canal, Franck Cappello, Fabien Chaix, Guillaume Colin de Verdiere, Said Derradji, Stefano Di Carlo, Christian Engelmann, Ignacio Laguna, Miquel Moreto, Onur Mutlu, Lazaros Papadopoulos, Olly Perks, Manolis Ploumidis, Bezhad Salami, Yanos Sazeides, Dimitrios Soudris, Yiannis Sourdis, Per Stenstrom, Samuel Thibault, Will Toms, Osman Unsal. "Towards Resilient EU HPC Systems: A Blueprint". European HPC Resilience Initiative. White paper. Online: https://resilientHPC.eu/blueprint2020. April 2020.
[video]

2019

MEMSYS Darko Zivanovic, Pouya Esmaili-Dokht, Sergi Moré, Javier Bartolome, Paul Carpenter, Petar Radojković and Eduard Ayguadé. "DRAM Errors in the Field: A Statistical Approach". In Proceedings of the International Symposium on Memory Systems (MEMSYS). Washington, DC, US. October 2019
MEMSYS Kazi Asifuzzaman, Mikel Fernandez, Petar Radojković, Jaume Abella and Francisco J. Cazorla. "STT-MRAM for Real-Time Embedded Systems: Performance and WCET Implications". In Proceedings of the International Symposium on Memory Systems (MEMSYS). Washington, DC, US. October 2019
MEMSYS Shang Li, Rommel Verdejo, Petar Radojković and Bruce Jacob. "Rethinking Cycle-accurate DRAM Simulation". In Proceedings of the International Symposium on Memory Systems (MEMSYS). Washington, DC, US. October 2019
SIGMETRICS Milan Radulovic, Rommel Sánchez Verdejo, Paul Carpenter, Petar Radojković, Bruce Jacob, Eduard Ayguadé. "PROFET: Modeling System Performance and Energy Without Simulating the CPU". In Journal Proceedings of the ACM on Measurement and Analysis of Computing Systems (SIGMETRICS). Volume 3, Issue 2, June 2019. [ GitHub ]

2018

MEMSYS Rommel Sánchez Verdejo, Kazi Asifuzzaman, Milan Radulovic, Petar Radojković, Eduard Ayguadé, Bruce Jacob. "Main Memory Latency Simulation: The Missing Link". In Proceedings of the International Symposium on Memory Systems (MEMSYS). Washington, DC, US. October 2018.
SBAC-PAD Milan Radulovic, Kazi Asifuzzaman, Darko Zivanovic, Nikola Rajovic, Guillaume Colin de Verdiere, Dirk Pleiter, Manolis Marazakis, Nikolaos Kallimanis, Paul Carpenter, Petar Radojković, Eduard Ayguadé. "Mainstream vs. Emerging HPC: Metrics, Trade-offs and Lessons Learned". In Proceedings of the 30th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD). Lyon, France. September 2018.
EURO-PAR Milan Radulovic, Kazi Asifuzzaman, Paul Carpenter, Petar Radojković, Eduard Ayguadé. "HPC Benchmarking: Scaling Right and Looking Beyond the Average". In Proceedings of the 24th International European Conference on Parallel and Distributed Computing (Euro-Par). Turin, Italy. August 2018.

2017

MEMSYS Kazi Asifuzzaman, Rommel Sánchez Verdejo, Petar Radojković. "Enabling a reliable STT-MRAM main memory simulation". In Proceedings of the International Symposium on Memory Systems (MEMSYS). Washington, DC, US. October 2017.
HPCS Rommel Sánchez Verdejo, Petar Radojković. "Microbenchmarks for Detailed Validation and Tuning of Hardware Simulators". In Proceedings of the International Conference on High Performance Computing and Simulation (HPCS). Genoa, Italy. September 2017.
DSD Rigo et al. "Paving the way towards a highly energy-efficient and highly integrated compute node for the Exascale revolution: The ExaNoDe approach". In Proceedings of the Euromicro Conference on Digital System Design (DSD). August 2017.
ACM TACO Darko Zivanovic, Milan Pavlovic, Milan Radulovic, Hyunsung Shin, Jongpil Son, Sally A. McKee Paul M. Carpenter, Petar Radojković, Eduard Ayguadé. "Main Memory in HPC: Do We Need More, or Could We Live with Less?". In ACM Transactions on Architecture and Code Optimization (TACO). 14 (1), March 2017. [bibtex]

2016

MEMSYS Darko Zivanovic, Milan Radulovic, German Llort, David Zaragoza, Janko Strassburg, Paul M. Carpenter, Petar Radojković, Eduard Ayguadé. "Large-Memory Nodes for Energy Efficient High-Performance Computing". In Proceedings of the International Symposium on Memory Systems (MEMSYS). Washington, DC, US. October 2016. [bibtex]

- The best paper award.
MEMSYS Kazi Asifuzzaman, Milan Pavlovic, Milan Radulovic, David Zaragoza, Ohseong Kwon, Kyung-Chang Ryoo, Petar Radojković. "Performance Impact of a Slower Main Memory: A case study of STT-MRAM in HPC". In Proceedings of the International Symposium on Memory Systems (MEMSYS). Washington, DC, US. October 2016. [bibtex]
IEEE TC Petar Radojković, Paul M. Carpenter, Miquel Moretó Vladimir Čakarević, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky and Mateo Valero. "Thread Assignment in Multicore/Multithreaded Processors: A Statistical Approach". In IEEE Transactions on Computers (TC), 65 (1). January 2016. [appendix] [bibtex]

- Featured article of the month, IEEE TC January 2016. [video]

2015

MEMSYS Milan Radulovic, Darko Zivanovic, Daniel Ruiz, Bronis R. de Supinski, Sally A. McKee, Petar Radojković, Eduard Ayguadé. "Another Trip to the Wall: How Much Will Stacked DRAM Benefit HPC?". In Proceedings of the International Symposium on Memory Systems (MEMSYS). Washington, DC, US. October 2015. [bibtex]
ICPC Milan Pavlovic, Milan Radulovic, Alex Ramirez, Petar Radojković . "Limpio: LIghtweight MPI instrumentatiOn". In Proceedings of the IEEE 23rd International Conference on Program Comprehension (ICPC). Florence, Italy. May 2015. [bibtex]

2014

IPDPS Ivan Grasso, Petar Radojković, Nikola Rajović, Isaac Gelado, Alex Ramirez. "Energy Efficient HPC on Embedded SoCs: Optimization Techniques for Mali GPU". In Proceedings of the 28th IEEE International Parallel and Distributed Processing Symposium (IPDPS). Phoenix, Arizona, US. May 2014. [bibtex]

2013

IEEE TPDS Petar Radojković, Vladimir Čakarević, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky and Mateo Valero. "Thread Assignment of Multithreaded Network Applications in Multicore/Multithreaded Processors". In IEEE Transactions on Parallel and Distributed Systems (TPDS), 24 (4). December 2013. [bibtex]

2012

MICRO Petar Radojković, Paul M. Carpenter, Miquel Moretó, Alex Ramirez and Francisco Cazorla. "Kernel Partitioning of Streaming Applications: A Statistical Approach to an NP-complete Problem". In Proceedings of 45th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-45). Vancouver, Canada. December 2012. [bibtex]
ASPLOS Petar Radojković, Vladimir Čakarević, Miquel Moretó, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky and Mateo Valero. "Optimal Task Assignment in Multithreaded Processors: A Statistical Approach". In Proceedings of 17th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-2012). London, UK. March 2012. [bibtex]
- The article is published also in ACM SIGARCH Computer Architecture News 40 (1), March 2012.
ACM TACO Petar Radojković, Sylvain Girbal, Arnaud Grasset, Eduardo Quiñones, Sami Yehia and Francisco J. Cazorla. "On the Evaluation of the Impact of Shared Resources in Multithreaded COTS Processors in Time-Critical Environments". In ACM Transactions on Architecture and Code Optimization (TACO), 8 (4). January 2012. [bibtex]

2010

PPoPP Petar Radojković, Vladimir Čakarević, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky and Mateo Valero. "Thread to Strand Binding of Parallel Network Applications in Massive Multi-threaded Systems". In Proceedings of 15th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming (PPoPP-2010). Bangalore, India. January 2010. [bibtex]
- The article is published also in ACM SIGPLAN Notices 45 (5), May 2010.

2009

MICRO Vladimir Čakarević, Petar Radojković, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky and Mateo Valero. "Characterizing the Resource Sharing Levels in the UltraSPARC T2 Processor". In Proceedings of 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42). New York City, US. December, 2009. [bibtex]

2008

SBAC-PAD Petar Radojković, Vladimir Čakarević, Javier Verdú, Alex Pajuelo, Roberto Gioiosa, Francisco J. Cazorla, Mario Nemirovsky and Malero Valero. "Measuring Operating System Overhead on CMT Processors". In Proceedings of 20th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD). Campo Grande, Brazil. October, 2008. [bibtex]

Zivanovic et al. "Main Memory in HPC: Do We Need More or Could We Live with Less?".
TACO 2017.

@inproceedings{Zivanovic:Main-memory-in-HPC-TACO-2017,
author = {Zivanovic, Darko and Pavlovic, Milan and Radulovic, Milan and Shin, Hyunsung and Son, Jongpil and Mckee, Sally A. and Carpenter, Paul M. and Radojkovi\'{c}, Petar and Ayguad{\'e}, Eduard},
title = {Main Memory in HPC: Do We Need More or Could We Live with Less?},
booktitle = {ACM Transactions on Architecture and Code Optimization (TACO)},
volume = {14},
number = {1},
month = mar,
year = {2017},
}

×

Zivanovic et al. "Large-Memory Nodes for Energy Efficient High-Performance Computing".
MEMSYS 2016.

@inproceedings{Zivanovic:Large-Memory-Nodes_MEMSYS-2016,
author = {Zivanovic, Darko and Radulovic, Milan and Llort, Germ\'{a}n and Zaragoza, David and Strassburg, Janko and Carpenter, Paul M. and Radojkovi\'{c}, Petar and Ayguad{\'e}, Eduard},
title = {{Large-Memory Nodes for Energy Efficient High-Performance Computing}},
booktitle = {Proceedings of the Second International Symposium on Memory Systems (MEMSYS '16)},
year = {2016},
}

×

Assifuzzman et al. "Performance Impact of a Slower Main Memory: A case study of STT-MRAM in HPC".
MEMSYS 2016.

@inproceedings{Asifuzzaman:STT-4-HPC_MEMSYS-2016,
author = {Asifuzzaman, Kazi and Pavlovic, Milan and Radulovic, Milan and Zaragoza, David and Kwon,
Ohseong and Ryoo, Kyung-Chang and Radojkovi\'{c}, Petar},
title = {Performance Impact of a Slower Main Memory: A Case Study of STT-MRAM in HPC},
booktitle = {Proceedings of the Second International Symposium on Memory Systems (MEMSYS '16)},
year = {2016},
}

×

Radojkovic et al. "Thread Assignment in Multicore/Multithreaded Processors: A Statistical Approach".
IEEE TC 2016.

@article{Radojkovic:ThareadAssignment-ToC2016,
author={Radojkovi{\'c}, P. and Carpenter P. M. and Moret\'{o) M. and \v{C}akarevi\'{c}, V. and Verd\'{u}, J. and Pajuelo, A. and Cazorla, F. J. and Nemirovsky, M. and Valero, M.},
journal={IEEE Transactions on Computers (TC)},
title={{Thread Assignment in Multicore/Multithreaded Processors: A Statistical Approach}},
issue_date = {January 2016},
volume = {65},
number = {1},
month = jan,
year = {2016},
}

×

Radulovic et al. "Another Trip to the Wall: How Much Will Stacked DRAM Benefit HPC?".
MEMSYS 2015.

@inproceedings{Radulovic:MemoryWall,
title = {{Another Trip to the Wall: How Much Will Stacked DRAM Benefit HPC?}},
booktitle = {{Proceedings of the International Symposium on Memory Systems (MEMSYS)}},
year = {2015},
author = {Radulovic, Milan and Zivanovic, Darko and Ruiz, Daniel and de Supinski, Bronis R. and McKee, Sally A. and Radojkovi\'{c}, Petar and Ayguad{\'e}, Eduard},
location = {Washington, DC, US},
}

×

Pavlovic et al. "Limpio: LIghtweight MPI instrumentatiOn".
ICPC 2015.

@inproceedings{Pavlovic:Limpio,
title = {{Limpio: LIghtweight MPI instrumentatiOn}},
booktitle = {{Proceedings of the IEEE 23rd International Conference on Program Comprehension (ICPC)}},
year = {2015},
author = {Pavlovic, Milan and Radulovic, Milan and Ramirez, Alex and Radojkovi\'{c}, Petar},
url = {http://www.bsc.es/computer-sciences/computer-architecture/memory-systems/limpio}, s
location = {Florence, Italy},
}

×

Grasso et al. "Energy Efficient HPC on Embedded SoCs: Optimization Techniques for Mali GPU".
IPDPS 2014.

@inproceedings{Grasso:MaliGPU,
title = {{Energy Efficient HPC on Embedded SoCs: Optimization Techniques for Mali GPU}},
booktitle = {Proceedings of the 28th IEEE International Parallel and Distributed Processing Symposium (IPDPS)},
year = {2014},
author = {Grasso, I. and Radojkovi{\'c}, P. and Rajovi{\'c} N. and Gelado I. and Ramirez A.},
location = {Phoenix, Arizona, US},
}

×

Radojković et al. "Thread Assignment of Multithreaded Network Applications in Multicore/Multithreaded Processors".
TPDS 2013.

@article{Radojkovic:ThreadAssignment,
author={Radojkovi{\'c}, P. and \v{C}akarevi\'{c}, V. and Verd\'{u}, J. and Pajuelo, A. and Cazorla, F. J. and Nemirovsky, M. and Valero, M.},
journal={IEEE Transactions on Parallel and Distributed Systems (TPDS)},
title={{Thread Assignment of Multithreaded Network Applications in Multicore/Multithreaded Processors}},
issue_date = {December 2013},
volume = {24},
number = {12},
month = dec,
year = {2013},
}

×

Radojković et al. "Kernel Partitioning of Streaming Applications: A Statistical Approach to an NP-complete Problem".
MICRO 2012.

@inproceedings{Radojkovic:KernelPartitioning,
title = {{Kernel Partitioning of Streaming Applications: A Statistical Approach to an NP-complete Problem}},
booktitle = {Proceedings of the 45th International Symposium on Microarchitecture (MICRO-45)},
year = {2012},
author = {Petar Radojkovi\'{c} and Paul M. Carpenter and Miquel Moret\'{o} and Alex Ramirez and Francisco J. Cazorla},
location = {Vancouver, Canada},
}

×

Radojković et al. "Optimal Task Assignment in Multithreaded Processors: A Statistical Approach".
ASPLOS 2012.

@inproceedings{Radojkovic:TaskAssignment,
author = {Radojkovi\'{c}, Petar and \v{C}akarevi\'{c}, Vladimir and Moret\'{o}, Miquel and Verd\'{u}, Javier and Pajuelo, Alex and Cazorla, Francisco J. and Nemirovsky, Mario and Valero, Mateo},
title = {{Optimal Task Assignment in Multithreaded Processors: A Statistical Approach}},
booktitle = {Proceedings of the 17th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)},
location = {London, UK},
year = {2012},
}

×

Radojković et al. "On the Evaluation of the Impact of Shared Resources in Multithreaded COTS Processors in Time-critical Environments".
TACO, January 2012.

@article{Radojkovic:MT-COTS,
author = {Radojkovi\'{c}, Petar and Girbal, Sylvain and Grasset, Arnaud and Qui\~{n}ones, Eduardo and Yehia, Sami and Cazorla, Francisco J.},
title = {{On the Evaluation of the Impact of Shared Resources in Multithreaded COTS Processors in Time-critical Environments}},
journal = {ACM Transactions on Architecture and Code Optimization (TACO)},
issue_date = {January 2012},
volume = {8},
number = {4},
month = jan,
year = {2012},
}

×

Radojković et al. "Thread to Strand Binding of Parallel Network Applications in Massive Multi-threaded Systems".
PPoPP 2010.

@inproceedings{Radojkovic:ThreadBinding,
author = {Radojkovi\'{c}, Petar and \v{C}akarevi\'{c}, Vladimir and Verd\'{u}, Javier and Pajuelo, Alex and Cazorla, Francisco J. and Nemirovsky, Mario and Valero, Mateo},
title = {{Thread to Strand Binding of Parallel Network Applications in Massive Multi-threaded Systems}},
booktitle = {Proceedings of the 15th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)},
year = {2010},
pages = {},
location = {Bangalore, India},
}

×

Cakarević et al. "Characterizing the Resource-Sharing Levels in the UltraSPARC T2 Processor".
MICRO 2009.

@inproceedings{Cakarevic:T2Characterization,
author = {\v{C}akarevi\'{c}, Vladimir and Radojkovi\'{c}, Petar and Verd\'{u}, Javier and Pajuelo, Alex and Cazorla, Francisco J. and Nemirovsky, Mario and Valero, Mateo},
title = {{Characterizing the Resource-Sharing Levels in the UltraSPARC T2 Processor}},
booktitle = {Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)},
location = {New York, US},
year = {2009},
}

×

Radojković et al. "Measuring Operating System Overhead on CMT Processors".
SBAC-PAD 2008.

@inproceedings{Radojkovic:OSoverhead,
author = {Radojkovi\'{c},, P. and \v{C}akarevi\'{c},, V. and Verd\'{u},, J. and Pajuelo,, A. and Gioiosa,, R. and Cazorla,, F. J. and Nemirovsky,, M. and Valero,, M.},
title = {Measuring {O}perating {S}ystem {O}verhead on {CMT} {P}rocessors},
booktitle = {Proceedings of the 20th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)},
year = {2008},
location = {Campo Grande, Brasil},
}

×