Petar Radojković

Email: petar.radojkovic at bsc.es
Phone: +34 93 41 37735
Web: www.PetarRadojkovic.com

Education

Ph.D. in Computer Architecture
"Improving the Effective use of Multithreaded Architectures:
Implications on Compilation, Thread Assignment, and Timing Analysis" [pdf]

Polytechnic University of Catalonia, Computer Architecture Department, Barcelona, Spain
Advisors: Francisco J.Cazorla, Mario Nemirovsky, Alex Pajuelo, Javier Verdú
 		2009 - 2013

M.Sc. in Computer Architecture, Networks, and Systems
"Measuring Operating System Overhead on CMT Processors" [pdf]

Polytechnic University of Catalonia, Computer Architecture Department, Barcelona, Spain
Advisors: Francisco J.Cazorla, Mario Nemirovsky, Alex Pajuelo, Javier Verdú
 		2007 - 2009

Diplomate Engineer in Computer Science (equivalent to M.Sc.)
"Application adaptive data cache memory"

Faculty of Electrical Engineering (Computer Science Department), Belgrade, Serbia 		2001 - 2006

Professional experience

Researcher
Computer Architecture group
Barcelona Supercomputing Center (BSC), Barcelona, Spain 		Aug 2013 - Present


Computer architecture group at BSC explores next-generation computer and system architectures for large-scale HPC and energy-efficient HPC systems.

Resident Student - Researcher
Computer Architecture Operating System Interface (CAOS) group
Barcelona Supercomputing Center (BSC), Barcelona, Spain 		2006 - 2013


CAOS group at BSC analyzes the impact of novel multicore multithreading processor architectures on high performance computing and real time systems.

Projects

Memory Systems for High Performance Computing
Barcelona Supercomputing Center - Samsung Electronics Co., Ltd. 		2013 - 2014


In this project, Samsung Electronics Co., Ltd. and Barcelona Supercomputing Center (BSC) collaborate in the field of memory systems for large-scale high performance computing (HPC) clusters. The goal of the project is to characterize memory requirements of state-of-the-art and future HPC systems, and to identify technology-related features that match these requirements.

Mont-Blanc
European scalable and power efficient HPC platform based on low-power embedded technology 		2011 - 2016


Mont-Blanc is an IP project within the Seventh Framework Programme of the European Union. The main objective of Mont-Blanc project is to design a new type of computer architecture capable of setting future global High Performance Computing (HPC) standards that will deliver Exascale performance while using 15 to 30 time less energy. This project is coordinated by the Barcelona Supercomputing Center (BSC) and has a budget of over 14 million, including over 8 million Euros funded by the European Commission.

Real-time Chip Multithreading (CMT) systems
Barcelona Supercomputing Center - Sun Microsystems Inc. 		2007 - 2009


In this project, Sun Microsystems Inc. and Barcelona Supercomputing Center collaborate in the area of Chip Multithreading (CMT) systems. The project focuses on characterization of UltraSPARC T1 and T2 processors and optimal process scheduling of low-layer network applications in CMT platforms based on these processors.

Internships

Netra DPS group, Sun Microsystems Inc.
Menlo Park, California, US
May - Aug 2008


Tasks done during the internship:
  • Performance measurements of Layer2/Layer3 network applications running in Netra DPS low-overhead environment on UltraSPARC T2 processors. This resulted in improvement in software and documentation developed by Netra DPS group at Sun Microsystems Inc.
  • Design of a set of benchmarks and execution of the experiments that demonstrated and quantified the overhead that hypervisor, Netra DPS, Linux, and Solaris OS introduce to the user applications running on UltraSPARC T1 processor.

    • Note: Netra DPS is a low-overhead environment developed by Oracle (Sun Microsystems Inc.). Netra DPS is very similar to real time operating systems. It is more predictable, provides more stable execution time, and introduces less overhead than fully-fledged operating systems like Linux or Solaris.

    Embedded Systems Lab, Thales Research & Technology
    Paris area, France     		Dec 2010 - March 2011

    During the internship, I developed a set of benchmarks (C and x86 assembly) that were used to quantify the worst-case slowdown that real-time applications may experience in shared resources of commercial-off-the-shelf (COTS) multithreaded processors. We used the benchmarks to understand how collision in shared processor resources can impact the timing properties of applications running in multithreaded environments.

    Technical skills and competencies

    Computer architecture

  • Good background in computer architecture and microarchitecture, especially in multicore multithreading processors
  • Specialist in UltraSPARC (Niagara) T1 and T2 processors
  • Experience in optimal process scheduling for multicore multithreading processors

    • Programming

  • C
  • SPARC and x86 assembly
  • Matlab
  • Shell scripting (Bash)

    • Performance and profiling tools

  • Using performance counters in Solaris OS and Netra DPS for application characterization and performance tuning
  • Solaris OS performance tools (cputrack, cpustat, pmap, trapstat, busstat)
  • Pin dynamic instrumentation tool

    • Mathematics and statistics

  • Good background in mathematics
  • Sampling methods
  • Statistical analysis and inference
  • Extreme Value Theory

    • Networking

  • Experience in development and performance tuning of network applications running in Netra DPS environment
  • Low layer (Layer2/Layer3), Deep packet inspection, Stateful applications

    • Low overhead runtime environments and real-time systems

  • Deep experience in working with Netra DPS (programming, execution of experiments, application profiling)
  • Understanding of real time systems and standards

    • Languages

  • Serbian: Native
  • English: Full professional proficiency
  • Spanish: Limited working proficiency

    • Grants

    Grant for development of university professors
    (Beca del programa de formación de profesorado universitario - FPU)
    Ministry of Education, Spain     		2009 - 2013
    Research grant
    Barcelona Supercomputing Center, Barcelona, Spain     		2006 - 2013
    Undergraduate student grant
    Ministry of Education, Republic of Serbia     		2002 - 2006

    Awards

    HiPEAC Paper Award


  • Petar Radojković, Paul M. Carpenter, Miquel Moretó, Alex Ramirez and Francisco Cazorla. "Kernel Partitioning of Streaming Applications: A Statistical Approach to an NP-complete Problem". In Proceedings of 45th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-45). Vancouver, Canada. December 2012.

  • Petar Radojković, Vladimir Čakarević, Miquel Moretó, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky and Mateo Valero. "Optimal Task Assignment in Multithreaded Processors: A Statistical Approach". In Proceedings of 17th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-2012). London, UK. March 2012.

  • Vladimir Čakarević, Petar Radojković, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky and Mateo Valero. "Characterizing the Resource Sharing Levels in the UltraSPARC T2 Processor". In Proceedings of 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42). New York City, US. December, 2009.

    • Publications


    For the list of the most relevant publications, please refer to the Publications tab of my webpage or to my Google-Scholar profile.